2011/12/5 8-bit加法器

程式碼

module top;
reg [7:0] A, B;
reg Cin;
wire[7:0] Sum;
adder8 M8(Cout, Sum, A, B, Cin);
initial
begin
A=8'd16;
B=8'd15;
Cin=1'd0;
end
endmodule
module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule
module adder2(Cout, Sum, A, B, Cin);
output Cout;
output [1:0] Sum;
input [1:0] A, B;
input Cin;
adder1 I1 (C0, Sum[0], A[0], B[0], Cin);
adder1 I2 (Cout, Sum[1], A[1], B[1], C0);
endmodule
module adder4(Cout, Sum, A, B, Cin);
output Cout;
output [3:0] Sum;
input [3:0] A, B;
input Cin;
adder2 I1 (C0, Sum[1:0], A[1:0], B[1:0], Cin);
adder2 I2 (Cout, Sum[3:2], A[3:2], B[3:2], C0);
endmodule
module adder8(Cout, Sum, A, B, Cin);
output Cout;
output [7:0] Sum;
input [7:0] A, B;
input Cin;
adder4 I1 (C0, Sum[3:0], A[3:0], B[3:0], Cin);
adder4 I2 (Cout, Sum[7:4], A[7:4], B[7:4], C0);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule