2011/11/28 4-bit加法器

程式碼

module top;

reg [3:0] A, B;
reg Cin;
wire[3:0] Sum;
adder4 M4(Cout, Sum, A, B, Cin);
initial
begin
A=4'd1;
B=4'd15;
Cin=1'd0;
end
endmodule
module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule
module adder2(Cout, Sum, A, B, Cin);
output Cout;
output [1:0] Sum;
input [1:0] A, B;
input Cin;
adder1 I1 (C0, Sum[0], A[0], B[0], Cin);
adder1 I2 (Cout, Sum[1], A[1], B[1], C0);
endmodule
module adder4(Cout, Sum, A, B, Cin);
output Cout;
output [3:0] Sum;
input [3:0] A, B;
input Cin;
adder2 I1 (C0, Sum[1:0], A[1:0], B[1:0], Cin);
adder2 I2 (Cout, Sum[3:2], A[3:2], B[3:2], C0);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2011/11/26 2-bit加法器

程式碼

module top;

reg [1:0] A, B;
reg Cin;
wire[1:0] Sum;

adder2 M2(Cout, Sum, A, B, Cin);

initial
begin
A=2'd3;
B=2'd3;
Cin=1'd0;
end

endmodule

module adder2(Cout, Sum, A, B, Cin);
output Cout;
output [1:0] Sum;
input [1:0] A, B;
input Cin;

adder1 I1 (C0, Sum[0], A[0], B[0], Cin);
adder1 I2 (Cout, Sum[1], A[1], B[1], C0);

endmodule

module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2011/11/26 2-bit多工器

程式碼

module top;
reg [1:0] A, B;
wire[1:0] OUT;
system_clock #100 clock1(SEL);
mux2 M1(OUT, A, B, SEL);
initial
begin
A=2'd2;
B=2'd1;
end
endmodule
module mux(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule
module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2011/11/7 1-bit加法器

程式碼

module top;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder1 M1(Cout, Sum, A, B, Cin);
endmodule

module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule