2011/11/7 1-bit加法器

程式碼

module top;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder1 M1(Cout, Sum, A, B, Cin);
endmodule

module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule